1. Field of the Invention
The present invention relates to a semiconductor memory production system, and a production method thereof, that infers the step in a wafer process that caused a defective semiconductor memory cell.
2. Description of the Related Art
In recent years, to improve the storage capacity of semiconductor memory, considerable effort has gone into the miniaturization of memory cells formed on chips.
If the development of a plurality of process steps (wafer process) necessary for the production of these miniaturized semiconductor memories and stabilization of these process steps are not performed rapidly, it is difficult to ship the required semiconductor memories at the time they are required.
Therefore, for the development and stabilization of each process step necessary for the production of semiconductor memory, it is essential to perform failure analysis of the semiconductor memory, and using the result obtained from this failure analysis repair the defect in the process step that caused the failure.
In general, judgment of whether the memory cells of a semiconductor memory are good or bad is performed such that predetermined data (xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d) is written to each memory cell bit by an LSI tester, then subsequently data is read out from this memory cell, and the two are compared to determine whether they match. The case where they match is designated as xe2x80x9cpass bitxe2x80x9d, the case of mismatch is designated as xe2x80x9cfail bitxe2x80x9d.
Various kinds of failure analysis are performed in respect of each individual semiconductor memory wherein the distribution condition of fail bits is generated and displayed in accordance with the arrangement of the memory cell array. This arrangement is called a fail bitmap, or just bitmap.
Japanese Examined Patent Application, Second Publication No. 6-18230 (hereunder referred to as First Prior Art) discloses a functional test performed automatically for all the chips in one wafer, and the test result is stored in a fail bit memory, and/or displayed on a screen and/or printed. At this time, for display in a limited area, the fail bit memory is divided into nxc3x97n blocks, and each block indicates the existence of a fail bit. Furthermore, when the contents of the fail bit memory are stored on an external storage device, to save memory capacity, one bit in one word (byte) corresponds to one bit of memory.
For example, with a 128 M bit semiconductor memory, the bitmap is 16 Mbytes for one chip. For one wafer (200 chips), 3.2 Gbytes of memory capacity is required, and for 1 lot (50 wafers), 160 Gbytes. Furthermore, if divided into 88 blocks, the memory capacity is 2.5 Gbytes per one lot, and the memory capacity can be reduced to {fraction (1/64)}th.
Japanese Unexamined Patent Application, First Publication No. 7-85697 (hereunder referred to as Second Prior Art) discloses a method of performing rapid failure analysis. In a memory map of a conventional semiconductor memory, fail bits with different failure modes, which have been caused by different failure causes, are mixed. As a result, the addresses are displayed as fail bits with different failure causes mixed in the abovementioned xe2x80x9cfail bitmapxe2x80x9d, which makes it difficult for a designer to identify the xe2x80x9cfailure modexe2x80x9d generated based on this xe2x80x9cfail bitmapxe2x80x9d, and further to infer the cause of the defect.
Here, xe2x80x9cfailure modexe2x80x9d means a unique fail bit distribution condition that appears in the case where a semiconductor memory having a specific failure, such as a defect etc., is tested in a predetermined condition, and it is known from experience that it shows different distribution conditions depending on the failure cause. For example, it includes a single bit failure in which there exists no fail bit before and after a target fail bit, a pair bit failure in which there exists a series of two fail bits, line failure (data line failure, or word line failure) in which there are more than three continuous bits and the like. Furthermore, the aforementioned xe2x80x9cfail bitmapxe2x80x9d is known as one of the devices suitable for identifying the distribution condition of fail bits.
Moreover, with the development of mass storage in recent semiconductor memory, this fail bitmap develops into a vast amount of data. Consequently, even if the First Prior Art is applied, it is difficult to output (print, display by CRT) the whole semiconductor memory as a fail bitmap at one time, which makes the operation of identifying the failure mode complicated. Furthermore, when analyzing the cause of the failure mode, the occurrence conditions must be analyzed for each individual fail bit. Therefore, there are also problems in that as the abovementioned xe2x80x9cfail bitmapxe2x80x9d becomes larger, the bitmap processing time in this analysis operation is greatly increased, and the analysis efficiency is reduced.
On the other hand, for a method to display the whole memory easily, a display method of a so-called xe2x80x9ccompressed bitmapxe2x80x9d in that the fail bitmap is summarized is proposed in the First Prior Art. In this compressed bitmap, a plurality of bits in memory is converted into one unit of a compressed bit, and the object fail bitmap is compressed by a predetermined ratio. The display method using this compressed bitmap can display the distribution condition of the fail bits of the whole memory map concerned. However, the detail of the occurrence conditions cannot be detected (for example, it cannot be judged whether the digest bit displays one fail bit or a plurality of fail bits). Consequently, to analyze the cause of failure, one to one display of the xe2x80x9cfail bitmapxe2x80x9d is required, so that the failure mode analysis operation by a designer remains complicated.
To solve these problems, in the Second Prior Art, firstly a test is performed under predetermined measurement conditions. In the case where it is judged to be defecty, fail bit data are obtained. Here, in most cases the obtained fail bit data are fail bit data of compound failure modes in which a plurality of failure causes are intermixed. Therefore, an algorithm that detects a specific xe2x80x9cfailure modexe2x80x9d as a target is generated by a combination of address theory and the like, with which specific failure mode data are extracted, and fail bit data corresponding to the specific failure mode are obtained from the fail bit data initially obtained.
From the fail bit data in which various types of failure modes are intermixed, firstly pair bit failure mode is extracted, which is further classified into even number-odd number defect address pairs, or odd number-even number pairs. Then, if there is no pair bit defect, the defect is classified as a single bit failure address. If a series of defecty bits exists, it is classified as a line failure mode. By classifying in this manner, a failure corresponding to a specific failure mode can be extracted, hence it is easy to identify the occurrence conditions of the specific failure. Furthermore, the fail bitmap can be classified by failure mode for display at wafer scale.
With the Second Prior Art, the memory capacity can be small in comparison with the bitmap. However, the memory capacity changes greatly by failure mode. For example, with a 128 M bit semiconductor memory, 27 bytes are required to display one bit address. In a supposed case where one k byte of fail bits are scattered in one chip, 27 kbytes of memory capacity is required. For one wafer (260 chips) 675kbytes, and for one lot (50 wafers) 33 Mbytes of memory capacity is required. Furthermore, in the case where the fail bits are all pair defects, the memory capacity becomes half of this, so that 17 Mbytes of memory capacity is required.
Moreover, with the Second Prior Art, to extract the failure mode, a vast amount of time is required. For example, in the case where one k byte of fail bits exists, the algorithm that is shown in the drawing in the publication must be repeated thousands of times.
The following publication describes a method for estimating a defecty process step in a manufacturing process by utilizing defect information and the like that are detected by the above method.
Japanese Unexamined Patent Application, First Publication No. 11-45919 (hereunder referred to as Third Prior Art) discloses, where a semiconductor substrate (wafer) is manufactured by a manufacturing line comprising a plurality of manufacturing equipment and required manufacturing processes (process steps), a method based on: a test step for testing the locations at which defects occur on each semiconductor substrate with regard to a plurality of semiconductor substrates manufactured; a failure distribution image data creation step for creating failure distribution image data, in which the failure location data on each semiconductor substrate tested by the test step is assigned a coordinate on the image data composed of grid-like picture elements set on the semiconductor substrate, and the number of failures for each grid-like picture element on the image data is summed for a plurality of semiconductor substrates; a failure analysis step that compares the failure distribution image data created by the failure distribution image data creation step with a case data base of a plurality of prepared failures and can investigate and estimates the cause of a failure occurrence.
For example, as shown in FIG. 23, if the failure distribution of a wafer 100 is in a pattern 311, by collating with a history data base created in the past for analysis purposes, it can be estimated that there is a failure cause in step A, and if it is in a pattern 313, that there is a cause in step C.
Furthermore, in the case where there is a step in which one lot is processed by single wafer processing in a plurality of the same type of manufacturing equipment, as shown in FIG. 24, if the failure distribution of the pattern 315 is larger than the pattern 314, depending on the manufacturing machine, it can be estimated that there is a cause in a manufacturing machine B.
In this manner, by knowing the distribution of defective cells on the wafer, and the distribution of the wafers in this lot, it is possible to infer the process step in which a memory cell becomes defective.
Japanese Unexamined Patent Application, First Publication No. 10-339943 (hereunder referred to as Fourth Prior Art) discloses a semiconductor memory manufacturing method having a step for performing a stepper type projection exposure using masks or reticules, wherein the chip coordinates are used to identify the chip location on the exposed semiconductor wafer, and it is judged whether the defect concerned is caused by a mask or reticule or not, from the chip coordinate data of the defecty chips that are distributed on the exposed semiconductor wafer, so that the location of a defect on the mask or reticule can be detected easily in a short period.
The stepper type exposure equipment operates by printing the pattern on a reticule 101 onto the wafer 100. At this time, as shown in FIG. 25, to reduce the number of exposures, a plurality of chips (4 chips in the figure) is reduced and exposed at the same time. By exposing the reticule 101 on the wafer 100 successively, a pattern is formed on the whole wafer.
For example, as shown in FIG. 25, in the case where the semiconductor memory on the wafer 100 is periodically judged to be defecty, it is estimated that it is caused by the mask or reticule 101, assuming that four semiconductor memory patterns (exposure units) are formed on the reticule 101, and that there is a defect in a specific region 101a. Printing on the resist on a wafer by a stepper using this reticule 101, as shown in FIG. 25, a specific location in each exposure unit on the wafer becomes periodically defective. Here, in FIG. 25, a chip marked xe2x80x9cxxe2x80x9d indicates a defecty chip.
Furthermore, in a lot that is processed at one time, in the case where defecty semiconductor memories are concentrated in the lower part 102 of the wafer 100 on all wafers contained in this lot, as shown in FIG. 26, it is estimated that the cause is an immersion type wet etching step, in which wafers stand vertically. The reason is considered to be as follows.
In wet etching during resist removal or oxide removal when a wafer is immersed in an etching liquid, the wafer is immersed from the lower part 102 and the upper part is submerged at the end. Therefore, the lower part of the semiconductor memory chip is immersed in the etching liquid for longer than the upper part, so that the period that it is etched by the etching liquid is also longer. Consequently, the pattern and thin film of the lower part 102 of the wafer is etched excessively.
Moreover, in the case where the number of semiconductor memories that are judged to be defecty on a wafer W1 is much higher compared with any other one of the wafers W2 through W25, it is estimated that the cause is that, as shown in FIG. 27, wafer W1 through W25 are placed in a line in phase direction in a boat 103 (at this time, the direction of an arrow marked A is the phase of the wafer W1 through W25) to perform wet etching. This is caused because, with regard to the surface that has semiconductor memory circuits on the wafer W1, the space is not enclosed compared with the surfaces of the other wafers, and hence a lot of activated etching liquid is applied.
In addition, for those other than the wafer W1 there is another wafer above the wafer surface, so that the supply of etching liquid is limited compared with the wafer W1.
Furthermore, in a drying process after submersion in the etching liquid, other cleaning processes and the like, differences depending on whether the processing face of a wafer is exposed at the front may appear.
As mentioned above, depending on the chip location on the wafer of a semiconductor memory that is judged to be defecty, and depending on the location of the a wafer in the lot, it is possible to infer which process step is the cause of failure.
Currently, with failure analysis of the process steps, estimation of the process step that is the cause of defecty semiconductor memory is performed based on test results in the wafer state.
Furthermore, a conventional failure analysis system detects the location of defecty semiconductor memory chips on a wafer based on bitmap information showing all defecty bits of the semiconductor memory chips input from the semiconductor test equipment,.
However, in the case of applying the failure analysis method shown in the Third and Fourth Prior Arts to a large capacity semiconductor memory, there is a problem in that a large amount of information must be dealt with. As mentioned above, in the case of storing one lot of bitmap information for a 128 M bit semiconductor memory with the First Prior Art, the amount of information is 2 to 3 Gbytes. To store such a large amount of information chronologically over a long period for analysis, it is difficult to process using a cheap personal computer, so an expensive information processing system must be introduced.
Furthermore, with the Second Prior Art, the amount of information differs greatly depending on the arrangement of fail bits, in other words, the failure mode. However, it is estimated to be about 15 K bytes per one chip, and 140 through 150 Mbytes per one lot. In the Second Prior Art, the amount of information can be reduced compared with the First Prior Art. However, to analyze the failure mode and compress the information, an expensive information processing system must be introduced and a time consuming arithmetic processing operation performed. Moreover with the Second Prior Art, with only a visual check of the failure mode analysis result, it cannot be judged whether the failure can be remedied by redundant circuits, or cannot be remedied.
Moreover, to reduce the amount of data storage per lot, it can be considered that only the yield data of each wafer needs to be stored chronologically in order to control lot yield.
In controlling just the yield of each wafer mentioned above, by the change in yield of lots stored periodically it is possible to detect a downward tendency in the yield caused by an abnormality of the whole wafer process, deterioration of manufacturing equipment and the like, so that failure analysis of the wafer process can be performed.
However, in process analysis or failure analysis to detect abnormal processes, since each chip on a defecty wafer is tested by a failure analyzer installed at a different location from the semiconductor production line, the number of analyses is increased.
Furthermore, with conventional failure analysis, a semiconductor memory that is judged defecty by a tester is selected and separated, and is retested by a failure analysis tester to analyze the cause of failure. Therefore, there is no notice until the yield in a wafer manufacturing line becomes worse, or a large amount of defecty product appears. Consequently, in the case where a large amount of defecty product appears, a situation occurs wherein semiconductor memories cannot be supplied to users.
The present invention has come about under such a background, with the object of providing a semiconductor memory production system that can maintain the data necessary for process analysis of each lot chronologically, and also enable failure analysis based on data already stored, without performing new measurements.
A first aspect of the invention is a semiconductor memory production test system in which there is provided: a wafer manufacturing line for manufacturing a plurality of semiconductor memory chips on a wafer using a plurality of kinds of wafer manufacturing equipment; a wafer tester for testing the electrical characteristics of the chips; a replacement address decision device for determining replacement addresses in a redundant memory section installed in the semiconductor memory based on the test results of the wafer tester; and an estimation section for estimating the cause of failures based on results of statistical processing of the replacement addresses, wherein the wafer manufacturing equipment causing failures is identified in the wafer manufacturing line and the cause of failures is removed.
A second aspect of the invention is a semiconductor memory production system according to the first aspect, wherein the estimation section is provided with a defect distribution analyzer for generating a replacement address distribution based on the replacement addresses, and a process defect estimation device for estimating process defects by comparing the replacement address distribution with previously stored defect distribution patterns.
A third aspect of the invention is a semiconductor memory production system according to the second aspect, wherein there is provided a defect distribution analyzer for generating a replacement number for specific replacement addresses in the wafer.
A fourth aspect of the invention is a semiconductor memory production test system according to the first aspect, wherein there is provided a defect distribution analyzer for generating a history of the replacement number.
A fifth aspect of the invention is a semiconductor memory production system, wherein semiconductor memories manufactured on wafers are tested, the test results are statistically processed to estimate the causes of defects, and the causes of the defects are removed from the wafer manufacturing equipment, wherein there is provided a semiconductor test section that tests the semiconductor memories and outputs a bitmap showing the fail or pass results judged from the address of each memory cell in a semiconductor memory, a replacement address decision section that extracts the bit address of a fail bit from the bitmap and, based on this bit address, determines a replacement word line and/or bit line address to be replaced with a redundant word line and/or redundant bit line in a redundant memory section installed in the semiconductor memory, and an estimation section for estimating process defects by statistical analysis based on the replacement number of the exchanged word lines or/and bit lines for each semiconductor memory, which is obtained based on the replacement addresses.
A sixth aspect of the invention is a semiconductor memory production system according to the first aspect, wherein the estimation section is provided with a fuse address setting section for generating fuse addresses showing sections disconnected by fuses that set the addresses of the redundant word lines and/or redundant bit lines for the replacement addresses, and an extraction section for extracting a replacement number of the word lines and/or bit lines exchanged for each semiconductor memory from the fuse addresses, and the distribution condition of each semiconductor memory chip for each wafer.
A seventh aspect of the invention is a semiconductor memory production system according to the first aspect, wherein the estimation section is provided with a pattern formation section that indicates each semiconductor memory chip on the wafer with a color or gradation corresponding to the replacement number.
An eighth aspect of the invention is a semiconductor memory production system according to the first aspect, characterized in that the estimation section compares the replacement number pattern with replacement number patterns stored in advance, which are generated for each process abnormality, and based on the result of this comparison, infers a specific process abnormality.
A ninth aspect of the invention is a semiconductor memory production method comprises: a wafer step for forming semiconductor memories on a wafer through a plurality of process steps; a wafer test step which examines the wafer in the wafer state to select non-defective products; a bitmap output step for outputting, as a result of the test, the address of each memory cell of the semiconductor memory, and a bitmap showing the pass and fail judgment; a replacement address decision step that extracts the bit address of a fail bit from the bitmap, and based on this bit address, determines a replacement word line and/or bit line address to be replaced with a redundant word line and/or redundant bit line in a redundant memory section installed in the semiconductor memory; and a process defect estimation step for estimating a process defect by statistical analysis based on the replacement number of the replaced word lines or/and bit lines for each semiconductor memory, which is obtained based on the replacement addresses.
A tenth aspect of the invention is a semiconductor memory production method according to the ninth aspect, wherein the process defect estimation step is provided with a fuse address setting section for generating fuse addresses showing sections disconnected by fuses that set the addresses of redundant word lines and redundant bit lines for the replacement addresses, and an extraction step for extracting a replacement number of the word lines and bit lines exchanged for each semiconductor memory from the fuse addresses, and the distribution condition of each semiconductor memory chip for each wafer.
An eleventh aspect of the invention is a semiconductor memory production method according to the ninth aspect, wherein the process defect estimation step is provided with a pattern formation section that indicates each semiconductor memory chip on the wafer with a color or gradation corresponding to the replacement number.
A twelfth aspect of the invention is a semiconductor memory production method according to the ninth aspect, wherein the process defect estimation step compares the replacement number pattern with replacement number patterns stored in advance, which are generated for each process abnormality, and based on the result of this comparison, estimates a specific process abnormality.